An integrated circuit may be developed by a team of designers using computer aided design software in conjunction with library cells provided by the semiconductor foundry. FIGS. 1-4 show memory cells from the user's perspective. These can also be referred to as logical memories. A generic core (e.g., macro) can include one or more memory built-in-self-test (MBIST) interfaces to test these logical memories. FIG. 1 shows the typical logical memory cell inside a generic core. As shown in FIGS. 2-4, the same logical memory inside a core may be configured as multiple physical memories or slices of physical memories. Each designer modifies these macros based on the specification for his part of the integrated circuit. A macro has a corresponding input file, e.g. core/macro specification file, which contains information describing the core/macro design, control signals, interface signals and logical array/memory definitions. Overall, manufacturing costs are reduced by testing and validating a design prior to fabrication to determine all physical memories in the core, their association with the logical memories and that their associated enabling signals physical memories are functioning properly.
FIG. 1 shows a logical memory that consists of 94 words, where each word is 100-bits wide. FIGS. 2-4 are possible implementations of the same logical memory. FIG. 2 and FIG. 3 implement the logical memory using 3 physical memories of different sizes while FIG. 4 implements the same logical memory using 6 physical memories. Each macro interface can consist of multiple logical memories. The physical configuration affects performance e.g. timing delays.
Further, each macro may have multiple interfaces. The name of a macro interface does not include a description of the underlying physical memories and their enabling signals because the same core can be configured in different fashions by each design team member who accesses the core. Without an accurate description, testing of the memories cannot be done properly or accurately which leads to field returns.
At this time, each of the integrated circuit designers manually creates the needed descriptions and provides this in a file to any tool so that these memories can be tested. This is time-consuming, error prone and may lead to issues as mentioned above that in some cases not all of the physical memories are getting tested.